The Use of SGMII SFP Module
2017-06-18
SGMII SFP transceiver module is used to connect Gigabit Ethernet to Fast Ethernet, such as between switch and switch interface, switched backplane applications and router/service interface. SGMII SFP meets SFP Multi-Source Agreement (MSA) and SFF-8472...
The Use of SGMII SFP Module
SGMII SFP is designed for 100BASE-LX applications of 10km with SMF. The transceiver consists of two sections: The standard SFP part and the PHY part built with SGMII interface. The optical output can be disabled by a TTL logic high-level input of Tx Disable, and the system also can disable the module via I2C. Tx Fault is provided to indicate that degradation of the laser. Loss of signal (LOS) output is provided to indicate the loss of an input optical signal of receiver or the link status with partner.
 
The system can also get the LOS (or link)/Disable/Fault information via I2C register access. The standard serial ID information Compatible with SFP MSA describes the transceiver capabilities, standard interfaces, manufacturer and other information. The host equipment can access this information via the 2-wire serial CMOS EEPROM protocol.
 
A typical chip-to-chip SGMII application may use between 12 to 48 full-duplex SGMII for 10/100/1000-Mbps Ethernet or Gigabit Ethernet links. For applications with SGMII links, the LVDS I/Os in Stratix V, Stratix IV, Stratix III, Cyclone V, Cyclone IV, Arria V, and Arria II GX FPGAs (fast speed grade) and HardCopy IV and HardCopy III ASICs (Altera devices with SGMII-capable LVDS I/Os) provide a preferred solution with low-power differential signaling capability, because these devices offer up to 132 LVDS transmitter and receiver pairs in the largest devices.
 
SGMII SFP is high performance, cost effective modules. This article is to Learn about the SGMII SFP Transceiver. The SGMII (Serial Gigabit Media Independent Interface) is a supplement of MII, a standard interface used to connect an Ethernet MAC-block to a PHY. It is utilized for Gigabit Ethernet (contrary to Ethernet 10/100 for MII).
 
It differs from GMII by its low-power and low pin count serial interface (commonly referred to as a SerDes). To carry frame data and link rate information between a 10/100/1000 PHY and an Ethernet MAC, SGMII uses a differential pair for data signals and for clocking signals, with both being present in each direction (i.e., transmit and receive), giving 8 signal lines in total.

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